Designing a MIPS Processor: From Single-Cycle to Pipelined Multi-Stage Architecture

Designing:

As part of my coursework in Computer Organization and Design, I and a partner developed a fully synthesized single-cycle MIPS processor using VHDL, constructing all components from the ground up. The processor was tested using assembly benchmarks to validate its performance. Following this, we extended the design into a multi-stage pipelined architecture, incorporating key features such as error detection, instruction forwarding, and logic to determine when a NOP (no operation) was necessary. The processor supported the standard MIPS instruction set and was optimized for efficient execution across a variety of computational tasks, demonstrating a strong understanding of processor design principles.

Monitoring and Validation:

Throughout the development process, each component of the processor was rigorously monitored at the bit level during simulation to ensure proper operation. Using waveform analysis, we tracked the behavior of crucial signals such as clock cycles, branch and jump signals, write enables, ALU output, and data flow between registers and memory. By observing changes in real-time, we were able to validate that the processor adhered to the expected behavior at every step. These detailed inspections allowed for the timely detection and resolution of issues like incorrect instruction execution, memory access errors, or branch mispredictions, ensuring that the processor's overall functionality met the design specifications.

Processor Performance Comparison:

To evaluate the performance of the single-cycle, software-scheduled, and hardware-scheduled pipelined MIPS processors, we ran benchmarks such as Grendle and Bubblesort, focusing on register reuse and optimization through either software-scheduled NOPs or hardware detection, including forwarders and flushing of the pipeline registers.

The single-cycle processor demonstrated a CPI (Cycles Per Instruction) of 1.00 for both benchmarks, executing Grendle in 85,529.5 ns and Bubblesort in 33,427.6 ns. The software-scheduled processor achieved a slight improvement, with a CPI of 1.15 for Grendle and 1.26 for Bubblesort, adjusting the execution time to 114,843 ns and 45,662 ns. Finally, the hardware-scheduled pipelined processor introduced significant pipeline optimizations, executing Grendle in 94,901.6 ns and Bubblesort in 39,754.4 ns, despite having a higher CPI of 2.11 and 2.26.

Although the pipelined processor's CPI was higher, its performance was nearly on par with the single-cycle design. This is because the pipeline allowed for faster clock cycles, breaking down the execution of instructions across multiple stages, rather than running everything in one cycle. While the CPI was higher due to pipeline hazards and stalls, our pipelined design, built by two students, was well-optimized. With further refinement, such as reducing pipeline stalls and improving instruction scheduling, the CPI could be driven closer to 1, resulting in significantly faster run times. This illustrates the power of pipelining in optimizing execution time, even with the added complexity.

My Takeaway

In this project, my partner and I collaboratively designed and built all components of a single-cycle MIPS processor using VHDL, gaining practical experience with hardware description languages. Together, we expanded the design into a multi-stage pipelined architecture, incorporating features like error detection and instruction forwarding. We learned the importance of bit-level precision, as every bit played a critical role in ensuring the processor functioned correctly. By working together through simulations and waveform analysis, we deepened our understanding of processor design and the trade-offs between simplicity and performance in different architectures.